0: buf
12: output_addr
16: _start
36: while
60: end---
mem[0..11]: 48 65 6c 6c 6f 0a 00 57 6f 72 6c 64 @"buf"
mem[12..15]: 84 00 00 00 @"output_addr"
mem[16..19]: Lui {rd = T0, k = 0} @_start
mem[20..23]: Addi {rd = T0, rs1 = T0, k = 12}
mem[24..27]: Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[28..31]: Addi {rd = T1, rs1 = T1, k = 0}
mem[32..35]: Addi {rd = T2, rs1 = Zero, k = 12}
mem[36..39]: Beqz {rs1 = T2, k = 24} @while
mem[40..43]: Addi {rd = T2, rs1 = T2, k = -1}
mem[44..47]: Lw {rd = T3, offsetRs1 = MemRef {mrOffset = 0, mrReg = T1}}
mem[48..51]: Sb {rs2 = T3, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[52..55]: Addi {rd = T1, rs1 = T1, k = 1}
mem[56..59]: J {k = -20}
mem[60..63]: Halt @end
mem[64..4095]: ( 00 )
/* comment */