0: output_addr
4: hello
256: _start
278: loop---
mem[0..3]: 84 00 00 00 @"output_addr"
mem[4..255]: 48 65 6c 6c 6f 0a 00 57 6f 72 6c 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @"hello"
mem[256..261]: MoveA {mode = Long, src = Immediate 0, dst = DirectAddrReg A1} @_start
mem[262..265]: MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}
mem[266..271]: Move {mode = Long, src = Immediate 4, dst = DirectDataReg D0}
mem[272..277]: Move {mode = Long, src = Immediate 12, dst = DirectDataReg D1}
mem[278..279]: MoveA {mode = Long, src = DirectDataReg D0, dst = DirectAddrReg A0} @loop
mem[280..283]: Move {mode = Byte, src = IndirectAddrReg 0 A0 Nothing, dst = DirectDataReg D2}
mem[284..287]: Move {mode = Long, src = DirectDataReg D2, dst = IndirectAddrReg 0 A1 Nothing}
mem[288..293]: Add {mode = Long, src = Immediate 1, dst = DirectDataReg D0}
mem[294..299]: Add {mode = Long, src = Immediate (-1), dst = DirectDataReg D1}
mem[300..305]: Bne {ref = 278}
mem[306..307]: Halt
mem[308..4095]: ( 00 )
/* comment */