0: input_addr
4: output_addr
8: _start---
mem[0..3]: 80 00 00 00 @"input_addr"
mem[4..7]: 84 00 00 00 @"output_addr"
mem[8..13]: MoveA {mode = Long, src = Immediate 0, dst = DirectAddrReg A0} @_start
mem[14..17]: MoveA {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectAddrReg A0}
mem[18..21]: Move {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectDataReg D0}
mem[22..23]: Not {mode = Long, dst = DirectDataReg D0}
mem[24..29]: And {mode = Long, src = Immediate 1, dst = DirectDataReg D0}
mem[30..35]: MoveA {mode = Long, src = Immediate 4, dst = DirectAddrReg A1}
mem[36..39]: MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}
mem[40..43]: Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg 0 A1 Nothing}
mem[44..45]: Halt
mem[46..4095]: ( 00 )
/* comment */