Simulation Results

/* variant: example factorial.s + factorial-5.yaml */

/* author: wrench */

/* wrench: 0.0.4.7-EDGE (6071349) Sat Jun 27 18:46:25 2026 +0200 */

/* comment */

Source: example/vliw-iv/factorial.s
Config: example/vliw-iv/factorial-5.yaml
ISA:    vliw-iv

/* assembler_code */

/* simulation_config */

/* simulation_result */

$ wrench --version
0.0.4.7-EDGE (6071349) Sat Jun 27 18:46:25 2026 +0200
/usr/local/bin/wrench --isa vliw-iv /app/example/vliw-iv/factorial.s -c /app/example/vliw-iv/factorial-5.yaml
ExitCode 0

---
# step-by-step
Isa {memOp = NopM, alu1Op = Lui {luiRd = T0, luiK = 0}, alu2Op = NopA, ctrlOp = NopC}	@_start
Isa {memOp = NopM, alu1Op = Addi {addiRd = T0, addiRs1 = T0, addiK = 0}, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = Lw {lwRd = T0, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = Lw {lwRd = T1, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = NopM, alu1Op = Addi {addiRd = T2, addiRs1 = Zero, addiK = 1}, alu2Op = NopA, ctrlOp = NopC}	@factorial_begin
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}}	@factorial_while
Isa {memOp = NopM, alu1Op = Lui {luiRd = T0, luiK = 0}, alu2Op = NopA, ctrlOp = NopC}	@factorial_end
Isa {memOp = NopM, alu1Op = Addi {addiRd = T0, addiRs1 = T0, addiK = 4}, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = Lw {lwRd = T0, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = Sw {swRs2 = T2, swOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}	
Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Halt}
---
# result
numio[0x80]: [] >>> []
numio[0x84]: [] >>> [120]

/* testcase_result */

0:	input_addr
4:	output_addr
256:	_start
312:	factorial_begin
326:	factorial_while
354:	factorial_end---
mem[0..3]: 	80 00 00 00	@"input_addr"
mem[4..255]: 	84 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00	@"output_addr"
mem[256..269]: 	Isa {memOp = NopM, alu1Op = Lui {luiRd = T0, luiK = 0}, alu2Op = NopA, ctrlOp = NopC} 	@_start
mem[270..283]: 	Isa {memOp = NopM, alu1Op = Addi {addiRd = T0, addiRs1 = T0, addiK = 0}, alu2Op = NopA, ctrlOp = NopC}
mem[284..297]: 	Isa {memOp = Lw {lwRd = T0, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}
mem[298..311]: 	Isa {memOp = Lw {lwRd = T1, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}
mem[312..325]: 	Isa {memOp = NopM, alu1Op = Addi {addiRd = T2, addiRs1 = Zero, addiK = 1}, alu2Op = NopA, ctrlOp = NopC} 	@factorial_begin
mem[326..339]: 	Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Beqz {beqzRs1 = T1, beqzK = 28}} 	@factorial_while
mem[340..353]: 	Isa {memOp = NopM, alu1Op = Mul {mulRd = T2, mulRs1 = T2, mulRs2 = T1}, alu2Op = Addi {addiRd = T1, addiRs1 = T1, addiK = -1}, ctrlOp = J {jK = -14}}
mem[354..367]: 	Isa {memOp = NopM, alu1Op = Lui {luiRd = T0, luiK = 0}, alu2Op = NopA, ctrlOp = NopC} 	@factorial_end
mem[368..381]: 	Isa {memOp = NopM, alu1Op = Addi {addiRd = T0, addiRs1 = T0, addiK = 4}, alu2Op = NopA, ctrlOp = NopC}
mem[382..395]: 	Isa {memOp = Lw {lwRd = T0, lwOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}
mem[396..409]: 	Isa {memOp = Sw {swRs2 = T2, swOffsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}, alu1Op = NopA, alu2Op = NopA, ctrlOp = NopC}
mem[410..423]: 	Isa {memOp = NopM, alu1Op = NopA, alu2Op = NopA, ctrlOp = Halt}
mem[424..4095]: 	( 00 )

/* comment: not found */

/* comment */

assembler_code =

simulation_config =

/* simulation_result */

simulation_log =

/* testcase_result */

failed_test_case =

execution_stats =

dump =