0: input_addr
4: output_addr
8: _start---
mem[0..3]: 80 00 00 00 @"input_addr"
mem[4..7]: 84 00 00 00 @"output_addr"
mem[8..11]: Lui {rd = T0, k = 0} @_start
mem[12..15]: Addi {rd = T0, rs1 = T0, k = 0}
mem[16..19]: Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[20..23]: Lw {rd = T1, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[24..27]: Addi {rd = T2, rs1 = Zero, k = 1}
mem[28..31]: Xor {rd = T1, rs1 = T1, rs2 = T2}
mem[32..35]: Lui {rd = T0, k = 0}
mem[36..39]: Addi {rd = T0, rs1 = T0, k = 4}
mem[40..43]: Lw {rd = T0, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[44..47]: Sw {rs2 = T1, offsetRs1 = MemRef {mrOffset = 0, mrReg = T0}}
mem[48..51]: Halt
mem[52..4095]: ( 00 )
/* comment */