Simulation Results

/* variant: example factorial-recursive-2.s + factorial-recursive-2.yaml */

/* author: wrench */

/* wrench: 0.0.4.7-EDGE (6071349) Sat Jun 27 18:46:25 2026 +0200 */

/* comment */

Source: example/m68k/factorial-recursive-2.s
Config: example/m68k/factorial-recursive-2.yaml
ISA:    m68k

/* assembler_code */

/* simulation_config */

/* simulation_result */

$ wrench --version
0.0.4.7-EDGE (6071349) Sat Jun 27 18:46:25 2026 +0200
/usr/local/bin/wrench --isa m68k /app/example/m68k/factorial-recursive-2.s -c /app/example/m68k/factorial-recursive-2.yaml
ExitCode 0

---
# step-by-step
0 0 MoveA {mode = Long, src = Immediate 8, dst = DirectAddrReg A7}	@_start
0 8 MoveA {mode = Long, src = IndirectAddrReg 0 A7 Nothing, dst = DirectAddrReg A7}	
0 512 MoveA {mode = Long, src = Immediate 0, dst = DirectAddrReg A0}	
0 512 MoveA {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectAddrReg A0}	
0 512 MoveA {mode = Long, src = Immediate 4, dst = DirectAddrReg A1}	
0 512 MoveA {mode = Long, src = IndirectAddrReg 0 A1 Nothing, dst = DirectAddrReg A1}	
0 512 Move {mode = Long, src = IndirectAddrReg 0 A0 Nothing, dst = DirectDataReg D0}	
5 512 Jsr {ref = 58}	
5 508 Link {addrReg = A6, offset = -4}	@factorial
5 500 Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
5 500 Ble {ref = 100}	
5 500 Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg (-4) A6 Nothing}	
5 500 Sub {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
4 500 Jsr {ref = 58}	
4 496 Link {addrReg = A6, offset = -4}	@factorial
4 488 Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
4 488 Ble {ref = 100}	
4 488 Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg (-4) A6 Nothing}	
4 488 Sub {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
3 488 Jsr {ref = 58}	
3 484 Link {addrReg = A6, offset = -4}	@factorial
3 476 Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
3 476 Ble {ref = 100}	
3 476 Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg (-4) A6 Nothing}	
3 476 Sub {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
2 476 Jsr {ref = 58}	
2 472 Link {addrReg = A6, offset = -4}	@factorial
2 464 Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
2 464 Ble {ref = 100}	
2 464 Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg (-4) A6 Nothing}	
2 464 Sub {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
1 464 Jsr {ref = 58}	
1 460 Link {addrReg = A6, offset = -4}	@factorial
1 452 Cmp {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	
1 452 Ble {ref = 100}	
1 452 Move {mode = Long, src = Immediate 1, dst = DirectDataReg D0}	@base_case
1 452 Unlk {addrReg = A6}	
1 460 Rts	
1 464 Move {mode = Long, src = IndirectAddrReg (-4) A6 Nothing, dst = DirectDataReg D1}	
1 464 Mul {mode = Long, src = DirectDataReg D1, dst = DirectDataReg D0}	
2 464 Unlk {addrReg = A6}	
2 472 Rts	
2 476 Move {mode = Long, src = IndirectAddrReg (-4) A6 Nothing, dst = DirectDataReg D1}	
2 476 Mul {mode = Long, src = DirectDataReg D1, dst = DirectDataReg D0}	
6 476 Unlk {addrReg = A6}	
6 484 Rts	
6 488 Move {mode = Long, src = IndirectAddrReg (-4) A6 Nothing, dst = DirectDataReg D1}	
6 488 Mul {mode = Long, src = DirectDataReg D1, dst = DirectDataReg D0}	
24 488 Unlk {addrReg = A6}	
24 496 Rts	
24 500 Move {mode = Long, src = IndirectAddrReg (-4) A6 Nothing, dst = DirectDataReg D1}	
24 500 Mul {mode = Long, src = DirectDataReg D1, dst = DirectDataReg D0}	
120 500 Unlk {addrReg = A6}	
120 508 Rts	
120 512 Move {mode = Long, src = DirectDataReg D0, dst = IndirectAddrReg 0 A1 Nothing}	
120 512 Halt
---
# result
numio[0x80]: [] >>> []
numio[0x84]: [] >>> [120]

/* comment: not found */

/* comment */

/* simulation_result */

/* testcase_result */

/* comment: not found */

/* comment */

assembler_code =

simulation_config =

/* simulation_result */

simulation_log =

/* testcase_result */

failed_test_case =

execution_stats =

dump =